Silicon Innovation Systems
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  • Home
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    • VLSI Design Services
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    • Analog Layout
    • Physical Design
    • Memory Layout Design
    • Standard Cell Layout
    • Analog Circuit Design
    • Fin-Fet Layout Design
    • ASIC Verification
    • RTL Coding & FPGA Design
    • Embedded Systems
  • Contact Us

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Welcome To Fin-Fet Layout Design Course

 Starting with the FinFet layouting of basic MOS transistors to industry standard project execution in FinFet technologies, the course develops to cover the more advanced techniques used in creating area efficient full custom digital & analog layouts.

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Course Highlights

CAD TOOLS

Mode Of Training

Mode Of Training

We are providing the best industry standard tools for designing.

Mode Of Training

Mode Of Training

Mode Of Training

We only provide offline courses to give the industrial experience to the students.

Expert Trainers

Course Eligibility

Course Eligibility

Our Trainers are having more than 15+ years of industry experience to provide the best quality training.

Course Eligibility

Course Eligibility

Course Eligibility

B.E/B.Tech/Diploma in ECE/EEE.

M.E/M.Tech/M.S in VLSI System Design/Embedded Systems/Digital Electronics

Fin-Fet Layout Design Course Curriculum

Module 1: Advanced Unix/Linux CMD's

Introduction and working knowledge of Unix/Linux commands.   File handling skills in UNIX/LINUX |SED & AWK.  Introduction to programming languages used in IC-Design.  

Module 2: Design for Manufacturability Checks (DFM)

Latch-up, Antenna Effect.   Electrical rule check (ERC) and Design rule check (DRC).  Electro-migration (EM), IR Drop & Self-Heat (SH).

Module 3: Deep sub-micron process challenges

Well proximity Effect (WPE), Length of Diffusion (LOD).   Shallow trench Isolation (STI). OSE/PSE.   Metal Density effect.  

Module 4: Analog Circuit Layout Design Techniques

Common centroid & Interdigitation matching techniques.   Critical signals shielding techniques.   Constraint & Module based floor planning techniques.   Guard / Seal ring techniques.  

Module 5: Custom Layout Techniques

STD Cell Layout design techniques.   I/O Layout design techniques.   Memory Layout Design techniques.  

Module 6: Layout Design of Critical Analog Circuits

Advanced/Critical Analog Circuits.   Complete Physical Verification Checks required for a Successful tape-out.  

Module 7: Industry standard Project Execution

Working on Critical Analog Circuits that are important in Industry. 

Module 8: Mock Interviews & Personality improvement

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Institute Of Silicon Innovation Systems

Office Address: #No 12,8th main, 4th cross, Bommanahalli Hosur main road, Bangalore 560068.

Phone: 08095574545

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Wed

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Thu

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Fri

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Sat

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Silicon Innovation Systems

#No 12,8th main, 4th cross, Bommanahalli Hosur main road, Beside Prashanth Hospital, Bangalore 560068

Email: hr@instituteofsis.com Mobile: 8095574545

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