Welcome To RTL Coding & FPGA Design Course

Module 1 : Basics of Unix/Linux

Introduction to Unix/Linux OS Architecture.   UNIX Directory Structures and Unix Commands.   UNIX Shells   LAB Exercises.  

Module 2: Digital logic Fundamentals and Advanced Digital Design

Importance and advantages of digital electronics.   Digital Number System, Binary logic gates & Boolean algebra.   Combinational and Sequential circuit designs.   Finite state machine optimization.  

Module 3: ASIC/FPGA/SOC Design Flow

What is FPGA? What is ASIC?   Overview of FPGA/ASIC/SOC design flow.   FPGA Vs ASIC comparison summary.   How to choose between FPGA or ASIC.  

Module 4: RTL Coding - Verilog HDL

Introduction to RTL coding.   Overview of digital design with Verilog HDL.   Design modeling with examples.   Tasks and functions.   RTL Simulation and Synthesis.   Creating power-friendly RTL & Timing analysis.   Module-level test bench development.   RTL design optimization techniques.  

Module 5: Programmable Logic Design

Read-only Memories (ROM)  PALs & PALs   CPLDs & FPGAs.  

Module 6: FPGA Design Example

FPGA Architecture.   Dual port memory - Example design.   FPGA design Flow   Bit file generation & downloading the Hex file to FPGA device.   FPGA validation through chip scope & DS5 debugger.   Project work and board bring up.  

Module 7: Advanced FPGA Concepts

Overview of 7 series FPGA architecture.   Introduction to Zynq FPGA-SoC --> SoCs with Hardware and Software programmability.   Efficient FPGA RTL coding for design synthesis & Implementation.  

Module 8 : Xilinx Design Implementation tools & Xilinx's Evalution board fo

Xilinx tool introduction & Installation.   RTL simulation - Qsim from Mentor graphics.   Hands-on experience in using the Vivado design suite for design synthesis and Implementation.   Hands-on experience in using chip scope and DS5 debugger for debugging functionality failures.  

Module 9: Mini & Major Projects on FPGA Device

Module 10: Soft Skill Development Programs