Signed in as:
filler@godaddy.com
Signed in as:
filler@godaddy.com
Physical design course mainly focused on giving hands-on practical experience in doing from RTL to GDSII, which includes many steps in complete cycle. We will work four industry standard projects.
We are providing the best industry standard tools for designing.
We only provide offline courses to give the industrial experience to the students.
Our Trainers are having more than 15+ years of industry experience to provide the best quality training.
B.E/B.Tech/Diploma in ECE/EEE.
M.E/M.Tech/M.S in VLSI System Design/Embedded Systems/Digital Electronics
1. Introduction and Working knowledge of UNIX/LINUX commands. 2. File handling skills in UNIX/LINUX. 3. Introduction to programming languages used in IC-Design.
1. MOSFET Operation, stick diagram, IC fabrication process. 2.Formation of Digital (NAND AND OR NOR etc.) logic using CMOS
1.Characterization of Digital standard cells and Library file information. 2. Technology File information, LEF file information, QRC Tech file process. 3.Basics RTL coding and RTL language like Verilog, VHDL, System Verilog.
1. Inputs and Outputs understanding. 2 .Constraints development and understanding. 3 .Optimization techniques (uniquify, preserve, flatten). 4 .DFT basics
1.Low power implementation techniques. 2. Sanity checks like check Design, lint report. 3. Derive environment features. 3.Generic, map, incremental. 4. Wire load model, PLE, Physical, Spatial.
1. Inputs and outputs understanding. 2. Intent and comparison understanding.
1 .Basic understanding of transition/slew, capacitance, leakage power, internal power ,and On-Chip-Variation (derate, AOCV, LVF). 2 .Library file difference NLDM, CCS, ECSM, LVF. 3 .Timing concepts understanding like setup, hold, recovery, removal, pulse width, clock gating check.
1.PLL jitter understanding and uncertainty calculations. 2.IO budgeting. 3.Different Timing Modes understanding. 4.ECO generation.
1.Floorplaning concepts and IO placement. 2.Power planning. 3.Placement strategies like region, fence, blockages, padding, bump, don't touch, filler gap. 4.DRV optimization, Buffer tree synthesis. 5.Clock tree synthesis and clock latency calculations.6. Routing design and optimization. 7. Antenna. 8. ECO Timing closure and implementation cycle.
1.Design Rule Checks understanding and importance. 2. Layout Versus Schematic and difference with respect to LEC. 3. Electrical Rule Checks. 4.IR Drop analysis - Static and Dynamic.
1.Industry Standard Physical Design Live Project
Add a footnote if this applies to your business
We love our customers, so feel free to visit during normal business hours.
Office Address: #No 12,8th main, 4th cross, Bommanahalli Hosur main road, Bangalore 560068
Phone: 08095574545
Mon | 09:00 am – 06:00 pm | |
Tue | 09:00 am – 06:00 pm | |
Wed | 09:00 am – 06:00 pm | |
Thu | 09:00 am – 06:00 pm | |
Fri | 09:00 am – 06:00 pm | |
Sat | 09:00 am – 06:00 pm | |
Sun | Closed |
Silicon Innovation Systems
#No 12,8th main, 4th cross, Bommanahalli Hosur main road, Beside Prashanth Hospital, Bangalore 560068
Email: hr@instituteofsis.com Mobile: 8095574545
Copyright © 2023 Silicon Innovation Systems - All Rights Reserved.
We use cookies to analyze website traffic and optimize your website experience. By accepting our use of cookies, your data will be aggregated with all other user data.
Please contact us: 08095574545