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Silicon Innovation Systems
Silicon Innovation Systems
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    • Home
    • Design Services
      • VLSI Design Services
    • Courses
      • Offered Courses
      • Analog Layout
      • Physical Design
      • Memory Layout Design
      • Standard Cell Layout
      • Analog Circuit Design
      • Fin-Fet Layout Design
      • ASIC Verification
      • RTL Coding & FPGA Design
      • Embedded Systems
    • Contact Us

  • Home
  • Design Services
    • VLSI Design Services
  • Courses
    • Offered Courses
    • Analog Layout
    • Physical Design
    • Memory Layout Design
    • Standard Cell Layout
    • Analog Circuit Design
    • Fin-Fet Layout Design
    • ASIC Verification
    • RTL Coding & FPGA Design
    • Embedded Systems
  • Contact Us

Welcome To Physical Design Course

Physical design course mainly focused on giving hands-on practical experience in doing from RTL to GDSII, which includes many steps in complete cycle. We will work four industry standard projects.

Course Curriculum

Physical Design

CAD TOOLS

Mode of Training

Mode of Training

We are providing the best industry standard tools for designing.

Mode of Training

Mode of Training

Mode of Training

We only provide offline courses to give the industrial experience to the students.

Expert Trainers

Course Eligibility

Course Eligibility

Our Trainers are having more than 15+ years of industry experience to provide the best quality training.

Course Eligibility

Course Eligibility

Course Eligibility

B.E/B.Tech/Diploma in ECE/EEE.

M.E/M.Tech/M.S in VLSI System Design/Embedded Systems/Digital Electronics

Physical Design Course Curriculum

Module 1: Basics of Unix/Linux

1. Introduction and Working knowledge of UNIX/LINUX commands.  2. File handling skills in UNIX/LINUX. 3. Introduction to programming languages used in IC-Design.  


Module 2:Basics of CMOS

1. MOSFET Operation, stick diagram, IC fabrication process. 2.Formation of Digital (NAND AND OR NOR etc.) logic using CMOS


Module 3:Design and Tech libraries

1.Characterization of Digital standard cells and Library file information. 2. Technology File information, LEF file information, QRC Tech file process. 3.Basics RTL coding and RTL language like Verilog, VHDL, System Verilog.


Module 4: Synthesis Part-1

1. Inputs and Outputs understanding. 2 .Constraints development and understanding. 3 .Optimization techniques (uniquify, preserve, flatten). 4 .DFT basics


Module 5: Synthesis Part-2

1.Low power implementation techniques. 2. Sanity checks like check Design, lint report. 3. Derive environment features. 3.Generic, map, incremental. 4. Wire load model, PLE, Physical, Spatial.


Module 6: Logical Equivalence

1. Inputs and outputs understanding. 2. Intent and comparison understanding.


Module 7: Static Timing Analysis Part-1

1 .Basic understanding of transition/slew, capacitance, leakage power, internal power ,and On-Chip-Variation (derate, AOCV, LVF). 2 .Library file difference NLDM, CCS, ECSM, LVF. 3 .Timing concepts understanding like setup, hold, recovery, removal, pulse width, clock gating check.


Module 8: Static Timing Analysis Part-2

1.PLL jitter understanding and uncertainty calculations. 2.IO budgeting. 3.Different Timing Modes understanding. 4.ECO generation.


Module 9: Physical Design

1.Floorplaning concepts and IO placement. 2.Power planning. 3.Placement strategies like region, fence, blockages, padding, bump, don't touch, filler gap. 4.DRV optimization, Buffer tree synthesis. 5.Clock tree synthesis and clock latency calculations.6. Routing design and optimization. 7. Antenna. 8. ECO Timing closure and implementation cycle.


Module 10: Physical Design Verification

1.Design Rule Checks understanding and importance. 2. Layout Versus Schematic and difference with respect to LEC. 3. Electrical Rule Checks. 4.IR Drop analysis - Static and Dynamic.


Module 11: Industry standard Project Execution

1.Industry Standard Physical Design Live Project


Module 12: Mock Interviews & Personality improvement

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Silicon Innovation Systems

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